Recently, many attempts have been made in which mobility of carriers (electrons and holes) moving at a channel region is improved by generating a strain in a channel to thereby improve an operation speed of a semiconductor device.
In general, the mobility of the hole is smaller than that of the electron in a transistor in which a region where impurity is doped into a silicon substrate is a channel. Accordingly, it is important in a design of a semiconductor integrated circuit device to improve the operation speed of a p-channel MOS transistor, of which carrier is the hole. It is known that the mobility of the hole improves by generating a uniaxial compressive strain at the channel region in the p-channel MOS transistor. Besides, it is principally pointed that the larger the compressive strain generated at the channel region is, the more the mobility of the hole increases, in the p-channel MOS transistor as stated above (Non-Patent Document 1).
In a formation of the p-channel MOS transistor, a method has been studied in which recesses are formed at a source region and a drain region of the silicon substrate, and SiGe layers containing boron (B) are epitaxially grown thereon.
It is preferable that an end portion of the SiGe layer is approximated to the channel region so as to enlarge the compressive strain generated at the channel region, in the method as stated above. However, a problem resulting from a short channel effect occurs in the conventional method only by approximating the SiGe layer to the channel region because the SiGe layer contains B being a p-type impurity.
Patent Document 1: Japanese Laid-open Patent Publication No. 2007-36205
Non-Patent Document 1: K. Mistry, et al., 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 50-51